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Single-Conversion DVB-H Tuner
Table 22. Offsets for Various Cutoff Frequencies
DESIRED 3dB CUTOFF FREQUENCY (TYPICAL) (MHz)
3.10
3.20
3.30
3.44
3.56
3.70
3.90
4.10
4.23
DC Offset Correction
Direct-conversion receivers are susceptible to DC offsets
that can limit linearity performance, as well as down-
stream data converter/demodulator dynamic range. The
MAX2165 includes on-chip fast-settling DC offset cancel-
lation circuitry that requires no off-chip components to
remove any undesirable DC offsets that are present in the
output signal.
The correction threshold can be programmed to four dif-
ferent values through the DC_TH[1:0] bits in the DC
Offset Control register (Table 13).
When offset correction is active, the correction circuitry
creates a highpass characteristic in the signal path with
the highpass cutoff frequency determining the offset
correction speed. This correction speed is program-
mable through the DC_SP[1:0] bits in the DC Offset
Control register.
For DVB-H applications, it is recommended that the DC
correction be performed once after the part is taken out of
shutdown, then disabled by programming the
DC_SP[1:0] bits to 00 (hold state). Disabling the DC offset
correction during signal reception prevents the highpass
characteristic introduced by the correction circuitry from
distorting the lower frequency components of the
received signal and allows for DC-coupling to the demod-
ulator. The only requirements for operation with DC-cou-
pling are that the receive frequency and baseband filter
setting remain constant after the one-time cancellation.
The typical time-sliced operating nature of DVB-H easily
allows for operation under these conditions.
The part can be configured to automatically perform DC
correction upon power-up through the use of the SHDN
and STBY pins. See the Power-Up Sequence section for
further information.
OFFSET TO BE ADDED TO ROM TABLE ENTRY 0x3 BEFORE
WRITING BACK INTO REGISTER 0xA
-6
-5
-4
-3
-2
-1
0
+1
+2
Power-Up Sequence and Shutdown Modes
Driving the SHDN pin low places the MAX2165 in hard-
ware shutdown mode, where all internal circuits are dis-
abled and the supply current decreases to less than
20μA. Driving SHDN low shuts the entire IC down
regardless of the state of the internal registers except for
the shutdown reference bit (SHDN_REF). Register set-
tings are maintained when the part comes out of shut-
down mode.
The MAX2165 also features a software-shutdown mode.
In software-shutdown mode, the individual bits of the
Shutdown register can be programmed to power down
the MAX2165 functional blocks. Program the Shutdown
register (Table 10) to 0xFF, the VCO[1:0] bits in the VCO
Control register (Table 11) to 00, and the DC_MO[1:0]
bits in the DC Offset Control register (Table 13) to 00 to
shut down the entire chip through the software.
The MAX2165 features a power-up sequencer that very
quickly removes the DC offset upon exiting hardware
shutdown mode. To enable the power-up sequence fea-
ture, connect STBY to ground while SHDN transitions
from low to high.
Power-Up Sequence
Holding STBY low while SHDN transitions high causes the
part to power up in a two-step process. In the first step,
the VCO and PLL power up and settle. The typical current
consumption during this first step is approximately 20mA.
In the second step, the entire signal path is powered up
and the RF_AGC voltage, the BB_AGC voltage, and the
DC correction are automatically overridden with DC offset
correction performed in less than 0.5ms. Once DC cor-
rection has been achieved the part is returned to its origi-
nally programmed state. The entire power-up process
completes in approximately 2ms.
20
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